The Edge Optimized Neural (EON) compiler is a powerful tool, included in Edge Impulse, that compiles machine learning models into highly efficient and hardware-optimized C++ source code. It supports a wide variety of neural networks trained in TensorFlow or PyTorch - and a large selection of classical ML models trained in scikit-learn, LightGBM or XGBoost. The EON Compiler also runs far more models than other inferencing engines, while saving up to 65% of RAM usage. This approach eliminates complex code, significantly reduces device resource utilization, and saves inference time. The EON Compiler also includes an additional option: The EON Compiler (RAM optimized), to better cater to diverse project requirements and constraints.
Some of the key advantages of EON Compiler, which include:

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Key Benefits of EON Compiler:

  • 25-65% less RAM
  • 10-35% less flash
  • Same accuracy as TFLite
  • Faster inference
The EON Compiler is specifically designed for Edge AI applications where speed is paramount. By focusing on minimizing inference time, this version of the EON Compiler ensures that neural network models can execute as quickly as possible, a critical requirement for real-time or near-real-time applications.

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EON Compiler (RAM optimized)

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The EON Compiler (RAM optimized) option further reduces memory usage, allowing AI models to run on even smaller microcontrollers (MCUs) without sacrificing the model’s accuracy or integrity. This is particularly beneficial for developers looking to minimize hardware costs and enhance the feasibility of deploying advanced AI in resource-constrained environments. We use a method to compute values directly as required, thus minimizing the need to store these results. This approach led to a substantial decrease in RAM usage, for a slightly higher latency cost. Please note that depending on your neural network architecture, we may not be able to provide this option, see the Limitations section.

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Examples

On-device resource usage - TFlite

What do these metrics mean?
  • Processing blocks: Here we can see the optimizations for the DSP components of the compiled model DSP components. e.g. Spectral Features, MFCC, FFT, Image, etc.
  • Learn Blocks: The performance of the compiled model on the device. Here we see the time it takes to run inference.
  • Latency: the time it takes to run the model on the device.
  • RAM: the amount of RAM the model uses.
  • Flash: the amount of ROM the model uses.
  • Accuracy: the accuracy of the model.

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How does it work?

The input of the EON compiler is a LiteRT (previously Tensorflow Lite) Flatbuffer file containing model weights. The output is a .cpp and .h files containing unpacked model weights and functions to prepare and run the model inference. Regular Tflite Micro is based on LiteRT (previously Tensorflow Lite) and contains all the necessary instruments for reading the model weights in Flatbuffer format (which is the content of .tflite file), constructing the inference graph, planning the memory allocation for tensors/data, executing the initialization, preparation and finally invoking the operators in the inference graph to get the inference results. The advantage of using the traditional Tflite Micro approach is very versatile and flexible. The disadvantage is that all the code for getting the model ready on the device is pretty heavy for embedded systems. To overcome these limitations, our solution involves performing resource-intensive tasks, such as reading the model from Flatbuffer, constructing the graph, and planning memory allocation directly on our servers. Subsequently, the EON compiler performs the generation of C++ files, housing the necessary functions for the Init, Prepare, and Invoke stages. These C++ files can then be deployed on the embedded systems, alleviating the computational burden on those devices. The EON Compiler (RAM Optimized) option adds, on top of the above, a novel approach by computing values directly as needed and minimizing the storage of intermediate results. This method leads to a significant decrease in RAM usage - sometimes at the cost of a slightly higher latency/flash - without impacting the accuracy of model predictions. In practice, we demonstrated this with our default 2D convolutional model for visual applications. By slicing the model graph into smaller segments, we managed to reduce the RAM usage significantly — by as much as 40 to 65% compared to LiteRT (previously Tensorflow Lite) — without altering the accuracy or integrity of the model’s predictions.

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Limitations

The EON Compiler, including the EON Compiler (RAM optimized) version, is a powerful tool for optimizing neural network projects. However, there are some important limitations to keep in mind: Unsupported Operators Not all operators are supported by our compiler. If your model includes an operator we don’t support, the compiler won’t be able to fully optimize your model. This means that certain complex operations within your model might prevent the compiler from working as efficiently as possible. Concerning the EON Compiler (RAM optimized) option, our slicing algorithm currently supports limited operators. For instance, if a standard convolutional model incorporates an unsupported operator in its architecture, the compiler will not be able to perform beyond that point. This limitation could restrict the application of our compiler to models that use only supported operations. Residual Layers We support models with certain types of residual layers—specifically, those that feed directly into a subsequent layer, like in MobileNet. However, if your model processes residuals in a more complex manner, the EON Compiler may not optimize it effectively.

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More metrics

In this section, we tested many different architectures. Some architectures may not be available with TFLite micro or with the EON-Compiler (RAM-Optimized) - see the limitations section.

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Image classification

RAM usage for Image classification architectures

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Object Detection

RAM usage for Object Detection architectures

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Keyword Spotting

RAM usage for Keyword Spotting architectures - 3960 features (MFE 1000ms 16kHz)

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Time series

RAM usage for time-series architectures